1. Field of the Invention
This invention relates to the field of integrated circuits and, more particularly, to generating a hardware description from a general purpose, high level programming language.
2. Description of the Related Art
The design of integrated circuits (ICs), digital logic intellectual property (IP), and particularly programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), typically begins with the development and validation of an algorithm which the IC is intended to implement. Presently, developers validate algorithmic designs by implementing algorithms in software programs written in a general purpose, high level language (HLL) such as C, C++, Java, or the like. HLLs provide designers with the ability to rapidly prototype an algorithm, explore the algorithm in further detail, and ultimately prove or validate that the algorithm is sufficient for the anticipated data processing for which the IC is being developed.
Once an algorithm has been validated, the HLL representation of the circuit design can be transformed into a hardware description of the circuit design using VERILOG, VHDL, or some other hardware description language alternative. Available software-based tools capable of performing such transformations generally attempt to map the HLL representation onto a particular target hardware architecture. One class of tools maps the HLL representation onto a hardware description which allows only a single data set to be processed at any given time. These architectures are referred to as “single process architectures”, and are characterized by a single threaded controlling state machine. When the circuit design is invoked, one data set must be completely processed before processing can begin on a next data set.
To overcome this limitation, another class of tools has been developed which supports the creation of multi-staged processing implementations. These tools rely on the designer's explicit inclusion of pre-defined constructs within the HLL program. These constructs control functions such as data movement into and out of the HLL representation and its various modules and further define threads of execution within the HLL program. Each explicitly defined thread can be converted into a processing stage of the multi-staged hardware description. The constructs controlling data movement specify scheduling information for the processing stages. While the ability to create multi-staged hardware implementations using these constructs is useful, it requires the designer to explicitly define each processing stage within the HLL program.
Still other tools implement a technique called multiple statically scheduled wavefronts. This technique calls for analyzing a single process architecture to determine whether a new data set can be introduced into the hardware implementation prior to the complete processing of a previous data set. If possible, a determination is made as to when a new data set can be introduced, for example every “N” clock cycles. The value of “N” typically is a conservative value which ensures that data is not overwritten within the resulting hardware implementation when new data is introduced. While designs created using this technique are more efficient than single process architectures, inefficiencies do exist. In particular, some data sets may be processed earlier than the value of “N” would otherwise allow. The hardware implementation, however, is unable to dynamically adjust to allow such new data sets to be processed earlier than the “N” clock cycle limitation.
It would be beneficial to provide a technique for developing a multi-staged hardware implementation from an HLL program in a manner that overcomes the limitations described above.